Spin transistor using spin-filter effect and nonvolatile memory using spin transistor

ABSTRACT

A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.

TECHNICAL FIELD

The present invention relates to a novel transistor, and moreparticularly to a transistor the output characteristics of which dependon the direction of spin of a carrier, and to a nonvolatile memorycircuit (nonvolatile memory) utilizing the transistor.

BACKGROUND ART

Conventionally, semiconductor memories used in electronic devices suchas microcomputers have mainly employed dynamic random access memories(DRAMs) from the viewpoint of operating speed and the degree of deviceintegration. It is difficult, however, for DRAMs to accommodate therecent demands for lower energy consumption and mobility because DRAMsconsume energy for memory storage purposes and the stored data is lostonce power supply is turned off. In order to address such demands, anovel memory is required that is nonvolatile as well as fast, highlyintegrated, and energy-saving.

Magnetoresistive random access memories (MRAMs) are now gainingattention as a next-generation memory with the nonvolatile property, inaddition to being capable of achieving operating speeds and levels ofintegration comparable to those of DRAMs. The MRAM stores information interms of the direction of magnetization of a ferromagnet. The relativemagnetization configuration of the information stored in the MRAM iselectrically sensed utilizing the giant magnetoresistance effect in aspin valve element, or the tunneling magnetoresistance (TMR) effect in amagnetic tunnel junction (MTJ). Since MRAMs utilize a ferromagnet, theycan hold information in a nonvolatile manner without consuming energy.

FIG. 17 shows a typical cell configuration of an MRAM utilizing a MTJ.As shown in FIG. 17(A), the MRAM comprises a 1-bit memory cellconsisting of one MTJ and one metal oxide semiconductor (MOS)transistor. The gate of the MOS transistor is connected to a wordlinefor sensing, the source is grounded, and the drain is connected to oneend of the MTJ. The other end of the MTJ is connected to a bitline.

As shown in FIG. 17(B), the MTJ has a tunnel junction structureconsisting of two ferromagnetic electrodes separated by a thininsulating film. The MTJ provides the TMR effect in which tunnelresistance varies depending on the relative magnetization configurationof the two ferromagnetic electrodes. The rate of change of TMR betweenthe case where the two ferromagnetic electrodes carry parallelmagnetization and the case where they carry antiparallel magnetizationis referred to as the TMR ratio, which is used for the evaluation of theTMR effect.

In the MRAM, information is stored in terms of the configuration ofmagnetization of the MTJ. Specifically, the relative magnetizationconfiguration of the two ferromagnetic electrodes is rendered eitherparallel or antiparallel using a composed magnetic field formed bymagnetic fields induced by currents that are caused to flow through thebitline and a wordline for writing (not shown) disposed perpendicular tothe bitline.

When sensing information stored in a particular cell, a voltage isapplied to a specific wordline for sensing connected to the cell so asto bring the MOS transistor into conduction, so that a current forsensing (to be hereafter referred to as a “drive current”) flows throughthe MTJ via a specific bitline connected to the cell. A voltage droppedacross the MTJ due to the TMR effect is then detected as an outputvoltage to sense the stored information.

SUMMARY OF THE INVENTION

Because the MRAMs based on MTJ employ ferromagnets, they arenonvolatile, energy-saving, and fast. In addition, their simple cellstructure renders the MRAMs suitable for high-density integration.However, before the MRAM can be realized as a next-generationnonvolatile memory, the following problems must be overcome.

(1) An MTJ exhibits two resistance values corresponding to parallel andantiparallel magnetization, and an MRAM detects these resistance valuesas output voltages by causing a drive current to flow through the MTJ.Thus, in order to obtain a high output voltage, the tunnel resistancemust be optimized by adjusting the thickness of the MTJ insulating film.However, since the TMR ratio also depends on the insulating filmthickness, optimization of the tunnel resistance is limited.

(2) Further, if the stored information is to be sensed accurately, theTMR ratio must be increased such that a high ratio of output voltages ofthe two magnetization configurations, i.e., parallel and antiparallel,can be obtained. In order to achieve a high TMR ratio, a ferromagnetwith a large spin polarization must be employed, and also the method offorming an insulating layer and its material and thickness, for example,must be optimized.

(3) In an MRAM utilizing a MTJ, the bias applied to the MTJ must beincreased in order to increase the operating speed. However, the MTJ hasthe fundamental problem that, as the voltage drop across theferromagnetic electrodes increases, the TMR ratio drops. Thus, the rateof change of output voltages due to TMR decreases as the voltage appliedto the MTJ increases. This phenomenon is inherently based on the TMReffect and hard to avoid as long as the configuration of magnetizationis sensed based solely on the TMR effect.

Thus, in order to detect information stored in a MTJ with highsensitivity, the output voltages must be optimized by adjusting theimpedance (junction resistance) of the MTJ. It is also necessary toincrease the output signal ratio of the two magnetizationconfigurations, namely, parallel and antiparallel, by increasing the TMRratio. At the same time, the TMR ratio must be prevented from beinglowered by biasing.

All of the aforementioned problems can be overcome if output signalcharacteristics can be freely designed in terms of peripheral circuitryregardless of the characteristics of the memory elements.

It is therefore an object of the present invention to provide anonvolatile memory in which information is stored in terms of themagnetization configuration of a ferromagnet contained in a transistorand in which the information is sensed using the output characteristicsof the transistor that depend on the direction of spin of the carrier.

In one aspect, the present invention provides a transistor comprising: aspin injector for injecting spin-polarized hot carriers by a spin-filtereffect; and a spin analyzer for selecting the thus injectedspin-polarized hot carriers by the spin-filter effect. Thus, the outputcharacteristics of the transistor can be controlled depending on thespin direction of the spin polarized hot carriers.

The spin injector preferably comprises a first ferromagnetic barrierlayer, a first nonmagnetic electrode layer joined to one end surface ofthe first ferromagnetic barrier layer, and a second nonmagneticelectrode layer joined to the other end surface of the firstferromagnetic barrier layer.

The spin analyzer preferably comprises: a second ferromagnetic barrierlayer; the second nonmagnetic electrode layer; and a third nonmagneticelectrode layer joined to the other end surface of the secondferromagnetic barrier layer. The second nonmagnetic electrode layer isjoined to one end surface of the second ferromagnetic barrier layer. Thesecond nonmagnetic electrode layer is common to the spin injector andthe spin analyzer.

The first and second ferromagnetic barrier layers preferably comprise aninsulating ferromagnetic semiconductor or a ferromagnetic insulator. Theenergy band edge of these ferromagnetic barrier layers is preferablyformed by an up-spin band or a down-spin band due to spin splitting. Thethickness of the second nonmagnetic electrode layer is preferably notgreater than the mean free path of the spin polarized hot carriers inthe second nonmagnetic electrode layer.

In the spin injector, the tunneling probability with respect to thecarriers with a spin parallel to the spin band forming the band edge ofthe first ferromagnetic barrier layer is large, whereas that withrespect to the carriers with an antiparallel spin is small. Thus,carriers with a parallel spin with the spin band forming the band edgeof the first ferromagnetic barrier layer can be injected from the firstnonmagnetic electrode to the second nonmagnetic electrode layer as hotcarriers.

On the other hand, the spin analyzer, due to the spin-splitting at theband edge of the second ferromagnetic barrier layer, allows thespin-polarized hot carriers to be transported to the third nonmagneticelectrode layer when the spin direction of the spin-polarized hotcarriers injected into the second nonmagnetic electrode is parallel tothe spin direction of the spin band at the band edge of the secondferromagnetic barrier layer. However, the spin analyzer does not allowthe spin-polarized hot carriers to be transported to the thirdferromagnetic electrode when the spin direction of the spin-polarizedhot carriers is antiparallel to that of the spin band at the band edgeof the second ferromagnetic barrier layer.

Thus, even under the same bias condition, the output characteristics ofthe transistor depend on the relative magnetization configuration of thefirst ferromagnetic barrier layer and second ferromagnetic barrierlayer. Specifically, the current transfer ratio or current gain is largewhen the first ferromagnetic barrier layer and second ferromagneticbarrier layer have parallel magnetization and it is small when they haveantiparallel magnetization.

The invention also provides a nonvolatile memory circuit in whichinformation can be stored in terms of the relative magnetizationconfiguration of the second ferromagnetic barrier layer and the firstferromagnetic barrier layer, and in which the information can be sensedusing the output characteristics of the transistor that depend on themagnetization configuration. In this memory circuit, a memory cell canbe configured with a single transistor.

In another aspect, the invention provides a nonvolatile memory circuitcomprising a spin transistor containing a ferromagnet and having outputcharacteristics that depend on the spin direction of the carriers, ameans for storing information in terms of the relative magnetizationconfiguration of the ferromagnet, and a means for electrically sensinginformation stored in the spin transistor using the outputcharacteristics.

The spin transistor preferably comprises at least one ferromagnet (to behereafter referred to as a “free layer”) in which the relativemagnetization configuration can be independently controlled, and atleast one ferromagnet in which the relative magnetization configurationis not changed (to be hereafter referred to as a “pin layer”). Storedinformation is retained in the form of a first state in which therelative magnetization configuration of the free layer is the same asthat of the pin layer, or a second state in which their magnetizationconfigurations are different.

Preferably, the spin transistor comprises: a first electrode structurefor injecting spin-polarized carriers; a second electrode structure forreceiving the spin-polarized carriers; and a third electrode structurefor controlling the amount of the spin-polarized carriers transportedfrom the first electrode structure to the second electrode structure.The pin layer and the free layer are preferably included in any of thefirst to third electrode structures.

The invention also provides a memory circuit comprising: theaforementioned spin transistors arranged in a matrix; a wordlineconnected to the third electrode structures; a first line connecting thefirst electrode structures to ground; and a bitline connected to thesecond electrode structures. A plurality of wordlines are extended inthe column direction, and a plurality of bitlines are extended in thedirection (the row direction) perpendicular to the column direction. Thespin transistors are disposed near the intersections of the wordlinesand bitlines.

In the aforementioned memory circuit, the magnetization in the freelayer can be reversed by a magnetic field induced by a current caused toflow through a first separate line and a second separate lineintersecting one another above the spin transistor in an electricallyinsulated manner, whereby the relative magnetization configurationbetween the free layer and the pin layer can be changed so thatinformation can be stored (or written).

It is possible to use the wordline and/or the bitline instead of thefirst separate line and/or the second separate line.

In the aforementioned memory circuit, information can be sensed usingthe output characteristics of the spin transistor when the free layerand the pin layer in the spin transistor have parallel magnetization.

The memory circuit may comprise an output terminal formed on one end ofeach bitline, and a second line branching from each bitline andconnected to a power supply via a load.

In this case, the information can be sensed from an output voltageobtained from the voltage drop across the load due to a current throughthe first and second electrode structures of the spin transistor, theoutput voltage depending on the relative magnetization configurationbetween the free layer and the pin layer.

Using the aforementioned circuit, a high-integration density andhigh-speed nonvolatile memory circuit can be provided in which theoutput voltages depending on the magnetization configuration within thetransistor can be designed via the load and power supply.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the structure of a spin-filter transistor according to anembodiment of the invention. FIG. 1 (A) shows a schematic cross section.FIG. 1 (B) shows an energy band diagram of a conduction band (or avalence band) of the structure shown in FIG. 1 (A), together with thespin direction of a spin band in the barrier layer.

FIG. 2 shows an energy band diagram in a case where a common-base biasvoltage is applied between the emitter (first nonmagnetic electrodelayer) and collector (third nonmagnetic electrode layer) of thespin-filter transistor of the present embodiment. FIG. 2 (A) shows acase where the relative magnetization configuration of the first andsecond ferromagnetic barrier layers is parallel. FIG. 2 (B) shows a casewhere the relative magnetization configuration of the first and secondferromagnetic barrier layers is antiparallel.

FIG. 3 shows the static characteristics of the spin-filter transistor ofthe present embodiment in a common-base configuration. The horizontalaxis shows collector-base voltage V_(CB) to the right and emitter-basevoltage V_(EB) to the left at the top of the figure. The vertical axisshows emitter current I_(E), base current I_(B), and collector currentI_(C). FIG. 3 (A) shows the characteristics in a case where themagnetization configuration between the ferromagnetic barrier layers ofthe emitter and collector is parallel, while FIG. 3 (B) shows thecharacteristics in the case of antiparallel magnetization.

FIG. 4 (A) shows an example of a memory cell utilizing a spin-filtertransistor 1 of the present embodiment. FIG. 4 (B) shows an example of amemory circuit. The vertical axis of FIG. 4 (C) shows collector currentI_(C), and the horizontal axis shows collector-emitter voltage V_(CE),together with the I_(C)-V_(CE) characteristics of the spin-filtertransistor 1 and a load line due to a load resistor.

FIG. 5 (A) shows an example of the output characteristics of acurrent-driven spin transistor. FIG. 5 (B) schematically shows anexample of the output characteristics of a voltage-driven spintransistor.

FIG. 6 (A) shows an example of a memory cell employing a voltage-drivenspin transistor of the present embodiment. FIG. 6 (B) shows an exampleof a memory circuit. The vertical axis of FIG. 6 (C) shows drain currentI_(D), and the horizontal axis shows drain-source voltage V_(DS), thefigure also showing the I_(D)-V_(DS) characteristics of a voltage-drivenspin transistor 150 and a load curve due to an active load in the samechart.

FIG. 7 shows an energy band diagram of an example of a hot-electrontransistor type spin transistor.

FIG. 8 shows an energy band diagram of an example of a hot-electrontransistor type spin transistor employing thermionic emission injection.

FIG. 9 shows an energy band diagram of an example of a hot-electrontransistor type spin transistor utilizing the spin-filter effect.

FIG. 10 shows an energy band diagram of an example of a tunnel basetransistor type spin transistor.

FIG. 11 shows a cross section of a MOS transistor type spin transistor.

FIG. 12 shows a cross section of a modulation-doped transistor type spintransistor.

FIG. 13 shows a cross section of an example of a MOS transistor typespin transistor comprising a ferromagnetic semiconductor channel.

FIG. 14 shows a cross section of an example of a spin transistorcomprising a ferromagnetic source, a ferromagnetic drain, and anonmagnetic insulating tunnel barrier disposed between the source andthe drain, wherein a gate insulating film and a gate electrode areformed on the tunnel barrier.

FIG. 15 shows a cross section of an example of a spin transistorcomprising a ferromagnetic source, a ferromagnetic drain or anonmagnetic drain, and an insulating ferromagnetic tunnel barrierdisposed between the source and drain, wherein a gate insulating filmand a gate electrode are formed on the tunnel barrier.

FIG. 16 (A) shows an example of a memory cell with a common-sourceconfiguration.

FIG. 16 (B) shows a cross section of a memory cell with a common-sourceconfiguration.

FIG. 17 (A) shows the structure of a conventional MRAM utilizing a MTJ.FIG. 17 (B) shows the operating principle of the MTJ.

BEST MODE FOR CARRYING OUT THE INVENTION

The transistor according to the present invention comprises a spininjector for injecting spin-polarized hot carriers having a specificspin direction, and a spin analyzer for selecting the thus injectedspin-polarized hot carries by their spin directions. The spin injectorcomprises a first ferromagnetic barrier layer with such a thicknessallowing for tunneling, such as Fowler-Nordheim tunneling or a directtunneling; a first nonmagnetic electrode layer joined to one end surfaceof the first ferromagnetic barrier layer; and a second nonmagneticelectrode layer joined to the other end surface of the firstferromagnetic barrier layer. The spin analyzer comprises a secondferromagnetic barrier layer; a second nonmagnetic electrode layer joinedto one end surface of the second ferromagnetic barrier layer; and athird nonmagnetic electrode layer joined to the other end surface of thesecond ferromagnetic barrier layer. The second nonmagnetic electrodelayer is common to the spin analyzer and the spin injector. Thethickness of the second nonmagnetic electrode layer is preferably notgreater than the mean free path of the spin-polarized hot carriers inthe nonmagnetic electrode layer.

When the above-described structure is compared with that of aconventional hot electron transistor, the first nonmagnetic electrodelayer and the first ferromagnetic barrier layer correspond to theemitter and the emitter barrier, respectively; the second nonmagneticelectrode layer corresponds to the base; and the second ferromagneticbarrier layer and the third nonmagnetic electrode layer correspond tothe collector barrier and the collector, respectively.

The first and second ferromagnetic barrier layers comprise an insulatingferromagnetic semiconductor or a ferromagnetic insulator. The energybands of these ferromagnetic barrier layers are spin-split by magneticexchange interaction, and only an up-spin band or a down-spin bandexists at the band edges due to this spin splitting. The energy width inwhich only one of the spin bands exists is referred to as a spin-splitwidth.

The spin-filter effect of the spin injector takes advantage of thefollowing fact. Namely, in the tunneling effect, such as Fowler-Nordheim(FN) tunneling or a direct tunneling, in which a voltage is applied tothe first ferromagnetic barrier layer via the first nonmagneticelectrode layer and the second nonmagnetic electrode layer, those of thecarriers in the first nonmagnetic electrode layer that have a spindirection corresponding to that of the spin band at the band end of thefirst ferromagnetic barrier layer (the spin direction being antiparallelto the magnetization of the first ferromagnetic barrier layer when thecarriers are electrons, or parallel to the magnetization of the firstferromagnetic barrier layer when the carriers are hole) have a largetunneling probability, whereas those with a spin direction that does notcorrespond (the spin direction being parallel to the magnetization ofthe first ferromagnetic barrier layer when the carriers are electrons,or antiparallel to the first ferromagnetic barrier layer when thecarriers are holes) have a small tunneling probability.

The spin-filter effect of the spin analyzer takes advantage of the factthat, when injecting spin-polarized hot carriers from the spin injectorinto the spin-split band of the second ferromagnetic barrier layer, thespin-polarized hot carriers are transported through the spin band in thesecond ferromagnetic layer and arrive at the third nonmagnetic electrodelayer when the spin direction of the injected spin-polarized hotcarriers is parallel to that of the spin band at the band edge of thesecond ferromagnetic barrier layer (where the first and secondferromagnetic barrier layers have parallel magnetization), whereas whenthe spin direction at the band edge of the second ferromagnetic barrierlayer is antiparallel to that of the spin-polarized hot carriers (wherethe first and second ferromagnetic barrier layers have antiparallelmagnetization), the spin-polarized hot carriers cannot be transportedthrough the second ferromagnetic barrier layer.

In this arrangement, the carriers in the first nonmagnetic electrodelayer with the spin direction parallel to that of the spin band at theband edge of the first ferromagnetic barrier are injected asspin-polarized hot carriers into the second nonmagnetic electrode layerby tunneling, such as Fowler-Nordheim tunneling or a direct tunneling.The transistor is biased such that the energy of the thus injectedspin-polarized hot carriers is larger than the energy of the spin bandedge of the second ferromagnetic barrier layer and smaller than theenergy of the spin band edge to which the spin-split width has beenadded. Since the thickness of the second nonmagnetic electrode layer isnot greater than the mean free path of the spin-polarized hot carriersin the second nonmagnetic electrode layer, the injected spin-polarizedhot carriers arrive at the second ferromagnetic barrier layer withoutlosing energy. In addition, the energy of the spin-polarized hotcarriers is larger than that of the spin band edge at the band edge ofthe second ferromagnetic barrier layer and is smaller than the energy ofthe spin band edge to which the spin-split width has been added.Therefore, when the spin direction of the injected spin-polarized hotcarriers is parallel to the spin direction of the spin band at the bandedge of the second ferromagnetic barrier layer, the spin-polarized hotcarriers are transported within the spin band by an electric fieldproduced in the second ferromagnetic barrier layer, and transported tothe third nonmagnetic electrode layer, producing a current that flowsbetween the third nonmagnetic electrode layer and the first nonmagneticelectrode layer.

On the other hand, when the spin direction of the injectedspin-polarized hot carriers is antiparallel to the spin direction of thespin band at the band edge of the second ferromagnetic barrier layer,the spin-polarized hot carriers are scattered (or reflected) by theboundary between the second nonmagnetic electrode layer and the secondferromagnetic barrier layer, producing a current that flows between thesecond nonmagnetic electrode layer and the first nonmagnetic electrodelayer.

Thus, depending on whether the relative magnetization configuration ofthe first ferromagnetic barrier layer and the second ferromagneticbarrier layer, namely, whether they are parallel or antiparallel, thecurrent that flows in the first ferromagnetic barrier layer can beswitched to a current that flows between the third nonmagnetic electrodelayer and the first nonmagnetic electrode layer via the secondferromagnetic barrier layer, or a current that flows between the secondnonmagnetic electrode layer and the first nonmagnetic electrode layer.Namely, the current through the second ferromagnetic barrier layer canbe controlled by the relative magnetization configuration of the firstferromagnetic barrier layer and the second ferromagnetic barrier layer.When compared with the operation of known common-base or common-emitterhot electron transistors or bipolar transistors, the above-describedoperation of the present embodiment corresponds to controlling thecollector current by means of the base current. However, in thetransistor of the present embodiment, the factor of amplification of thecollector current by the base current can be controlled by the relativemagnetization configuration of the first ferromagnetic barrier layer andthe second ferromagnetic barrier layer. Thus, the transistor of thepresent embodiment is capable of controlling the current gain, wherebycollector current can be controlled not only by the base current (or thebias voltage between the first and second nonmagnetic electrodes), butalso by the relative magnetization configuration of the firstferromagnetic barrier layer and the second ferromagnetic barrier layer.

Furthermore, when the coercive forces of the first ferromagnetic barrierlayer and the second ferromagnetic barrier layer are varied, or when therelative magnetization configuration of one of them is fixed, therelative magnetization configuration of the first ferromagnetic barrierlayer and the second ferromagnetic barrier layer can be changed to beparallel or antiparallel as desired by applying a magnetic field of anappropriate intensity such that the relative magnetization configurationof either the first ferromagnetic barrier layer or the secondferromagnetic barrier layer is reversed. Namely, information can bestored in the transistor.

Thus, a memory cell can be configured with the above-describedtransistor. An example of a nonvolatile memory utilizing the transistorof the present embodiment will be hereafter described. The secondnonmagnetic electrode layer of the transistor of the embodiment isconnected to a wordline, and the third nonmagnetic electrode layer ofthe transistor is connected to a bitline. The bitline is connected to apower supply via a load, and the first nonmagnetic electrode layer ofthe transistor is grounded. In this arrangement, when a specificwordline is selected and a bias is applied to the second nonmagneticelectrode layer, the output voltage (voltage that appears at the thirdnonmagnetic electrode) detected by selecting a specific bitline is seento vary depending on the relative magnetization configuration of thefirst ferromagnetic barrier layer and the second ferromagnetic barrierlayer of the transistor. Namely, when the relative magnetizationconfiguration are parallel, the output voltage becomes smaller, whilewhen the relative magnetization configuration is antiparallel, theoutput voltage becomes larger. Thus, the information that is stored canbe sensed on the basis of the magnitude of the output voltage.

In the above-described nonvolatile memory, the transistor of the presentembodiment is used as a common-emitter transistor, a power supply and aload are provided to the collector, and the collector voltage isobtained as the output voltage. Thus, using peripheral circuitry such asthe power supply and load, desired output voltage values can be obtainedwhen the first ferromagnetic barrier layer and second ferromagneticbarrier layer have parallel magnetization or when they have antiparallelmagnetization. Accordingly, the above-described nonvolatile memory canovercome the aforementioned problems of the MRAM based on MTJ, theproblems being that the tunnel resistance as well as output voltages aresmall, that the TMR ratio is so small that the information that isstored is hard to be distinguished, and that the ratio of outputvoltages decreases due to the applied bias.

In the following, the configuration and operation of the above-describedtransistor is described in greater detail with reference made to thedrawings. The transistor of the present embodiment will be hereafterreferred to as a “spin-filter transistor” for facilitating theunderstanding of the description of the invention.

FIG. 1 shows the configuration of a spin-filter transistor according tothe present embodiment. FIG. 1 (A) shows a schematic cross section. FIG.1 (B) shows an energy band of the conduction band (or the valence band)of the configuration shown in FIG. 1 (A), also showing the spindirection of the spin band in the barrier layer. When the carriers areholes, the direction of magnetization at the band edge corresponds tothe spin direction; when the carriers are electrons, the relativemagnetization configuration is opposite to that of the spin direction ofthe band edge.

A spin-filter transistor 1 according to the present embodiment comprisesa spin injector 5 comprising: a first ferromagnetic barrier layer 2; afirst nonmagnetic electrode layer 3 joined to one end surface of thefirst ferromagnetic barrier layer 2; and a second nonmagnetic electrodelayer 4 joined to the other end surface of the first ferromagneticbarrier layer 2. The spin-filter transistor 1 also comprises a spinanalyzer 8 comprising: a second ferromagnetic barrier layer 6; a secondnonmagnetic electrode layer 4 joined to one end surface of the secondferromagnetic barrier layer 6; and a third nonmagnetic electrode layer 7joined to the other end surface of the second ferromagnetic barrierlayer 6. As will be seen from FIG. 1 (A), the spin injector 5 and thespin analyzer 8 shares the second nonmagnetic electrode layer 4.

The first, second, and third nonmagnetic electrode layers 3, 4, and 7may be formed by a nonmagnetic metal, an n-type nonmagneticsemiconductor, or a p-type nonmagnetic semiconductor. The thickness ofthe second nonmagnetic electrode layer 4 is preferably not greater thanthe mean free path within the nonmagnetic electrode layer 4 of thespin-polarized hot carriers injected from the spin injector. By makingthe base width shorter than the mean free path, the current transferratio can be made 0.5 or greater, so that current amplification can beachieved.

The first and second ferromagnetic barrier layers 2 and 6 may comprisean insulating ferromagnetic semiconductor or a ferromagnetic insulator.The energy band of the ferromagnetic barrier layer is spin-split bymagnetic exchange interaction, such that an energy region is created atthe band edge where only an up spin or a down spin exists. Such aspin-polarized band is referred to as a spin band, and this energyregion band is referred to as a spin-split width Δ.

As shown in FIG. 1 (B), the solid lines with an arrow ↑ on theferromagnetic barrier layers 2 and 6 indicate the edge of the band wherean up spin can exist, namely, an up-spin band edge 9. The solid lineswith an arrow ↓ indicate the edge of the band where a down spin canexist, namely, a down-spin band edge 10. The region between the up-spinband edge 9 and the down-spin band edge 10 in FIG. 1 (B) is a regionwhere only an up spin can exist. A region with a higher energy than thatof the down-spin band edge 10 is a region where both up spin and downspin can exist. While FIG. 1 (B) shows a case where the spin band of upspin is lower than the spin band of down spin, the opposite state isalso possible.

The first ferromagnetic barrier layer 2 has a thickness such that thecarriers can be transmitted from the first nonmagnetic electrode layer 3to the second nonmagnetic electrode layer 4 by tunneling, such asFowler-Nordheim tunneling (to be hereafter referred to as “FNtunneling”) or a direct tunneling, in response to the application of avoltage to the first nonmagnetic electrode layer 3 and to the secondnonmagnetic electrode layer 4. A direct tunneling refers to thephenomenon in which the carriers directly pass through a thin potentialbarrier. The FN tunneling refers to the phenomenon in which thetunneling current due to a direct tunneling can be ignored up to acertain applied voltage and in which the carriers tunnel through thetriangular potential at the top of a potential barrier produced by theapplication of a voltage exceeding a certain value.

The voltage applied to the first nonmagnetic electrode layer 3 and thesecond nonmagnetic electrode layer 4 may be in the voltage range used inthe conventional memory circuit, such as on the order of several hundredmV to several volts. The second ferromagnetic barrier layer 6 needs tobe sufficiently thick that there is no thermionic emission of thecarriers or a current due to tunneling (the so-called leak current) fromthe second nonmagnetic electrode layer 4 to the third nonmagneticelectrode layer 7.

The nonmagnetic electrode layers 3, 4, 7 and the ferromagnetic electrodelayers 2 and 6 form the energy band structure shown in FIG. 1 (B). Solidlines 11 in the nonmagnetic electrode layer FIG. 1 (B) indicate theFermi energy of the metal, the Fermi energy of an n-type (p-type)semiconductor, or the energy at the bottom of the conduction band (atthe top of the valence band). The lower energy barrier in theferromagnetic barrier layers 2 and 6 corresponding to the solid lines 11at the nonmagnetic electrode layer is indicated by φ_(C), and thespin-split width is indicated by Δ. Although the ferromagnetic barrierlayers 2 and 6 may have different values of φ_(C) and Δ, the followingdescription concerns a case where the ferromagnetic barrier layers 2 and6 have the same values of φ_(C) and Δ.

In the case where the carriers are electrons, a nonmagnetic metal or ann-type semiconductor is used for the nonmagnetic electrode layers 3, 4,and 7, and an insulating ferromagnetic semiconductor or a ferromagneticinsulator is used for the ferromagnetic barrier layers 2 and 6. In thiscase, the up-spin band edge 9 and the down-spin band edge 10 areproduced by the spin splitting of the bottom of the conduction band ofthe ferromagnetic barrier layers 2 and 6. In the case where the carriersare holes, a p-type semiconductor is used for the nonmagnetic electrodelayer 3, 4, 7, and an insulating ferromagnetic semiconductor or aferromagnetic insulator is used for the ferromagnetic barrier layers 2and 6. In this case, the up-spin band edge 9 and the down-spin band edge10 of the ferromagnetic barrier layer 2 and 6 are produced by the spinsplitting of the top of the valence band.

Hereafter, the operating principle of the above-described spin-filtertransistor is described in detail. In the following description, thenotational system for the hot electron transistor will also be used forsimplicity's sake. Specifically, the first nonmagnetic electrode layer 3and the first ferromagnetic barrier layer 2 will be referred to as anemitter 21, the second nonmagnetic electrode layer 4 will be referred toas a base 22, the second ferromagnetic barrier layer 6 and the thirdnonmagnetic electrode layer 7 will be referred to as a collector 23, thefirst nonmagnetic electrode layer 3 will be referred to as an emitterelectrode 3, and the third nonmagnetic electrode layer 7 will bereferred to as a collector electrode 7. The following also concerns thecase where the carriers are electrons as an example (the case where thecarriers are holes will not be described because such a case issubstantially the same in terms of operating principle).

FIG. 2 shows energy band diagrams in a case where a common-base biasvoltage is applied between the emitter, base, and collector of thespin-filter transistor of the present embodiment. FIG. 2 (A) shows acase where the magnetization configurations of the first and secondferromagnetic barrier layers are parallel to each other, and FIG. 2 (B)shows a case where the magnetization configurations of the first andsecond ferromagnetic barrier layers are antiparallel to each other,corresponding to FIG. 2 (A). A bias voltage V_(EB) is applied acrossemitter 21 and base 22, and a bias voltage V_(CB) is applied across base22 and collector 23. The magnitude of V_(EB) is set such that therelationship (Φ_(C)<qV_(EB)<Φ_(C)+Δ) is satisfied, where q is theelementary charge.

The emitter 21 functions as a spin injector for injecting spin-polarizedhot electrons to base 22. Thus, when causing the carriers to passthrough the first ferromagnetic barrier layer 2 from the emitterelectrode 3 by tunneling using the bias voltage V_(EB), since theconduction band of the first ferromagnetic barrier layer 2 isspin-split, the barrier height for the up-spin electrode 24 and that forthe down-spin electrode 25 in the emitter electrode 3 are different.

Namely, in FIG. 2 (A), the barrier height for the up-spin electrode 24corresponds to the energy up to an up-spin band edge 9 of the firstferromagnetic barrier layer 2, or Φ_(C). The barrier height for thedown-spin electrode 25 corresponds to the energy up to a down-spin bandedge 10 of the first ferromagnetic barrier layer 2, or Φ_(C)+Δ. Thus, bycontrolling the base-emitter voltage, electrons with a spin for whichthe barrier height is lower, namely, an up spin, which correspond toelectrons 24 in the illustrated example, can be selectivelytunnel-injected to the base 22 (in a phenomenon called “spin-filtereffect”) as hot electrons.

The collector 23 of the spin-filter transistor functions as a spinanalyzer for selecting the direction of the spin-polarized hot electronsinjected into the base 22. Specifically, the spin-polarized electrons 26that have been rendered into hot electrons by the bias voltage V_(EB)and injected into the base 22 can arrive at the boundary between base 22and collector 23 without losing energy, or “ballistically,” because thewidth of base 22 is set to be not greater than the mean free path of thespin-polarized hot electrons 26. In the second ferromagnetic barrierlayer 6 of collector 23, there is also produced two barriers withdifferent barrier heights due to the spin splitting of the conductionband. As shown in FIG. 2 (A), when the magnetization configurations ofthe first and second ferromagnetic barrier layers 2 and 6 are parallelto each other, because the up-spin band edge 9 of the secondferromagnetic barrier layer 6 having a spin parallel to that of thespin-polarized hot electrons 26 is lower than the energy of thespin-polarized hot electrons 26, the spin-polarized hot electrons 26 aretransported to the collector electrode 7 across the second ferromagneticbarrier layer 6, thereby producing a collector current I_(C).

On the other hand, when the magnetization configurations of the firstand second ferromagnetic barrier layers 2 and 6 are antiparallel to eachother, as shown in FIG. 2 (B), spin-polarized hot electrons 27 with downspin are injected to a base 22. In this case, however, because thedown-spin band edge 10 of the second ferromagnetic barrier layer 6 withdown spin is higher than the energy of the spin-polarized hot electrons27, the spin-polarized hot electrons 27 cannot be transported throughthe conduction band of the second ferromagnetic barrier layer 6.Instead, they lose energy as they are subjected to spin-dependentscattering (or reflection) at the boundary between base 22 and collector23, resulting in a flow of base current I_(B).

Thus, the current transfer ratio of the current that flows from theemitter to the collector greatly differs depending on the relativemagnetization configuration of the first ferromagnetic barrier layer 2of emitter 22 and the second ferromagnetic barrier layer 6 of collector23. In other words, the current gain of collector current due to basecurrent greatly differs.

FIG. 3 shows the static characteristics of the spin-filter transistor ofthe present embodiment in a common-base configuration. The horizontalaxis shows collector-base voltage V_(CB) in the upper-right portion andemitter-base voltage V_(EB) to the left. The vertical axis shows emittercurrent I_(E), the base current I_(B), and collector current I_(C). FIG.3 (A) shows the static characteristics in a case where the magnetizationconfigurations of the ferromagnetic barrier layers of the emitter andthe collector are parallel. FIG. 3 (B) shows the static characteristicswhen the magnetization configurations are antiparallel. In both FIG. 3(A) and (B), α indicates the current transfer ratio, β indicates thecurrent gain, and the subscripts ↑↑ and ↓↑ indicate the parallel andantiparallel relative magnetization configuration, respectively, of theferromagnetic barrier layers of the emitter and collector.

As shown in FIG. 3 (A), when the magnetization configurations of theemitter and the collector are parallel, most of the emitter currentI_(E) can serve as the collector current I_(C). As shown in FIG. 3 (B),when the magnetization configurations are antiparallel, most of theemitter current I_(E) can serve as the base current I_(B). As in theknown hot electron transistors or bipolar transistors, the collectorcurrent I_(C) can be controlled by the base current I_(B) in thetransistor of the present embodiment. In addition, the current gain canbe controlled by the relative magnetization configuration of the firstand second ferromagnetic barrier layers.

The ferromagnetic barrier layer of the spin-filter transistor of thepresent embodiment may comprise a ferromagnetic semiconductor, such asEuS, EuSe, or EuO, for example. It may also comprise a ferromagneticinsulator, such as R₃Fe₅O₁₂ (where R is a rare-earth element). Thenonmagnetic electrode layer may comprise any material as long as it isnonmagnetic. Examples include metals, such as Al and Au, and nonmagneticsemiconductors, such as Si and GaAS, that have been doped with a highconcentration of impurity. When, for example, the ferromagnetic barrierlayer comprises EuS and the nonmagnetic electrode layer comprises Al,the barrier height Φ_(C) is 1.4 eV and the spin-split width Δ is 0.36eV. The spin-filter transistor of the present embodiment can be producedby a known method, such as molecular beam epitaxy, vacuum evaporation,or sputtering, using the above-described materials.

In the following, a nonvolatile memory comprising the spin-filtertransistor of the present invention as a memory cell will be described.

FIG. 4 (A) shows an example of a memory cell employing a spin-filtertransistor 1 of the present embodiment. In the memory cell shown in FIG.4 (A), a number of spin-filter transistors are arranged in a matrix,with the emitter terminals E grounded and the collector terminals C andthe base terminals B connected to a bitline BL for sensing and awordline WL for sensing, respectively. A wordline for writing intersectsa bitline for writing above the spin-filter transistors such that theselines are electrically insulated from other wires. The wordline forwriting and the bitline for writing may be combined with theaforementioned bitline BL for sensing and wordline WL for sensing, asshown in FIG. 4 (A). In the case of FIG. 4 (A), a memory cell can beformed by a single spin-filter transistor, and also a simple wiringarrangement can be adopted. Thus, the present memory cell arrangementmakes it possible to easily configure a layout suitable for high-densityintegration. The example shown in FIG. 4 (B) also adopts a similar cellarrangement.

With reference to FIG. 4(B), a memory circuit according to the presentembodiment will be described. In a memory circuit 41 of the presentembodiment, a second nonmagnetic electrode 4, which is the base of thespin-filter transistor 1 (FIG. 1), is connected to a wordline 42; athird nonmagnetic electrode 7, which is the collector electrode of thespin-filter transistor 1, is connected to a bitline 43; the bitline 43is connected to a power supply (V_(CC)) 45 via a load (R_(L)) 44; and afirst nonmagnetic electrode 3, which is the emitter electrode of thespin-filter transistor 1, is connected to ground. Although a pureresistance is used as the load in the illustrated example, an activeload consisting of a transistor may be used.

When sensing information stored in a specific memory cell, a specificwordline 42 is selected and a bias is applied across the emitter-basejunction, and a power supply voltage V_(CC) from the power supply 45 isapplied to the bitline 43 via the load resistance 44. Then, the storedinformation is sensed using the magnitude of an output voltage V_(O)that appears at the bitline 43. The vertical axis of FIG. 4 (C) showscollector current I_(C). The horizontal axis shows collector-emittervoltage V_(CE). The graph thus shows the I_(C)-V_(CE) characteristics ofthe spin-filter transistor and a load line 46 of the load resistance 44in the same chart.

The output voltage V_(O) is determined by the intersection of thesecharacteristics. Specifically, the output signals in the cases where themagnetization configuration between the first and second ferromagneticbarrier layers 2 and 6 is parallel and antiparallel would be V_(O↑↑) andV_(O↓↑), as shown in FIG. 4 (C). The absolute values of V_(O↑↑) andV_(O↓↑) and the ratio of V_(O↑↑) and V_(O↓↑) can be optimized by meansof circuit parameters (R_(L) and V_(CC)). Thus, using the nonvolatilememory device of the present embodiment, output signals of requiredmagnitudes and a required ratio of output signals can be obtainedwithout adjusting the structure of the elements themselves, as in a MTJ.

The spin-filter effect utilized by the transistor of the presentembodiment is provided by the spin band splitting of the ferromagnet,such that a higher spin selectivity can be obtained than is possiblewith the TMR effect of MTJ. When the base width is set to be no morethan the mean free path of the spin-polarized hot carriers, the currenttransfer ratio α (defined as being equal to I_(C)/I_(E)) can be 0.5 ormore when the relative magnetization configuration between the first andsecond ferromagnetic barrier layers is parallel. However, when therelative magnetization configuration is antiparallel, the currenttransfer ratio is extremely small. Thus, the change in the currenttransfer ratio between parallel magnetization and antiparallelmagnetization is even more amplified in terms of current gain β (definedas being equal to I_(E)/I_(B)). By optimizing the output signal usingthe above-described peripheral circuitry with reference to the outputcharacteristics of the spin-filter transistor that vary greatlydepending on the magnetization configuration, output signals of desiredabsolute values and their desired ratio can be easily obtained.

Hereafter a nonvolatile memory circuit utilizing a transistor (to behereafter referred to as a “spin transistor”) with outputcharacteristics that depend on the spin direction of the carriers isdescribed.

The memory circuit of the present invention relates to a nonvolatilememory circuit utilizing a spin transistor. A spin transistor includes aferromagnet such as a ferromagnetic metal or a ferromagneticsemiconductor. The output characteristics are changed by controlling thespin direction of the carriers depending on the magnetizationconfiguration of the ferromagnet. Information is stored in terms of themagnetization configuration of the ferromagnet inside the spintransistor, and the stored information is sensed using the outputcharacteristics of the transistor that reflect the magnetizationconfiguration inside the spin transistor. Using the spin transistor, a1-bit nonvolatile memory cell can be configured with a single spintransistor. Furthermore, the value of the output signal corresponding tothe stored information can be optimized by peripheral circuitryconnected to the memory cell.

Specifically, the spin transistor comprises at least one each of aferromagnet layer (free layer) capable of independently controlling therelative magnetization configuration using a magnetic field or the like,and a ferromagnet layer (pin layer) with a fixed relative magnetizationconfiguration or having a larger coercivity than that of the free layer.The output characteristics of the transistor can be controlled by therelative magnetization configuration of the free layer and the pin layereven under the same bias condition. By changing the relativemagnetization configuration of the free layer using a magnetic field,for example, the relative magnetization configuration of the free layerand the pin layer can be rendered into two configurations, namely,parallel or antiparallel. These two magnetization configurations areassociated with binary stored information.

In the spin transistor, based on a conduction phenomenon that variesdepending on the spin direction of the carrier, such as spin-dependentscattering, tunneling magnetoresistance effect, or spin-filter effect,output characteristics corresponding to the internal magnetizationconfiguration of the transistor can be obtained. The spin transistorcomprises a first electrode structure for injecting spin-polarizedcarriers, a second electrode structure for receiving the spin-polarizedcarriers, and a third electrode structure for controlling the quantityof spin-polarized carriers that are transported from the first electrodestructure to the second electrode structure.

The spin transistors operate on the same principle as that of theconventional transistors with the exception of the involvement of thespin-dependent conduction phenomenon. Thus, the spin transistors can beclassified into current-driven transistors such as bipolar transistors,and voltage-driven transistors such as field-effect transistors. Interms of the current-driven transistor, the first electrode structurecorresponds to the emitter, the second electrode structure correspondsto the collector, and the third electrode structure corresponds to thebase. The spin-filter transistor described with reference to the presentembodiment is a current-driven transistor. In terms of thevoltage-driven transistor, the first electrode structure corresponds tothe source, the second electrode structure corresponds to the drain, andthe third electrode structure corresponds to the gate. The outputcurrent in the spin transistor (collector current or drain current)changes depending on the magnetization configuration of the ferromagnetcontained in the spin transistor even under the same bias condition.

The details of the spin transistor will be described later. In thefollowing, the general output characteristics of a spin transistor and anonvolatile memory employing a spin transistor will be described. It isassumed in the following that the relative magnetization configurationbetween the free layer and the pin layer can be rendered parallel orantiparallel by applying a magnetic field to the free layer in the spintransistor. It is also assumed that the magnetization configuration canexist stably unless a magnetic field exceeding the coercivity of thefree layer is applied.

FIG. 5 (A) schematically shows an example of the output characteristicsof a current-driven spin transistor. As in a conventional current-driventransistor, although the collector current I_(C) can be controlled bythe magnitude of the base current I_(B), it is also dependent on themagnetization configuration of the ferromagnet contained in the spintransistor. In the example of FIG. 5 (A), even when the bias applied tothe spin transistor is the same (I_(B)=I_(B1)), the collector currentI_(C↑↑) in the case of parallel magnetization is large, whereas thecollector current I_(C↓↑) in the case of antiparallel magnetization issmall.

FIG. 5 (B) schematically shows an example of the output characteristicsof a voltage-driven spin transistor. As in a conventional field-effecttransistor, such as a MOS transistor, when the gate source voltage(V_(GS)) is smaller than the threshold value V_(T) (V_(GS)<V_(T)), thespin transistor is in an off state where hardly any drain current flows.Although the spin transistor conducts when a V_(GS) exceeding V_(T) isapplied, the drain current value differs depending on whether theferromagnets contained in the spin transistor have parallelmagnetization or antiparallel magnetization, even under the same biascondition (V_(GS)=V_(GS1)). In the case of FIG. 3 (B), the drain currentI_(D↑↑) is larger for parallel magnetization whereas the drain currentI_(D↓↑) is small for antiparallel magnetization.

Thus, the spin transistor, whether it is current-driven orvoltage-driven, can electrically detect the magnitude of the relativemagnetization configuration of the free layer and the pin layercontained in the device using the magnitude of the collector current orthe drain current. As mentioned above, the relative magnetizationconfiguration in the ferromagnet can exist stably unless a magneticfield exceeding the coercivity of the free layer is externally applied.Thus, the spin transistor can store binary information in a nonvolatilemanner by rendering the relative magnetization configuration of the freelayer and the pin layer contained in the device parallel orantiparallel. Therefore, using the spin transistor, a 1-bit nonvolatilememory cell can be configured with a single spin transistor.

In the following, a nonvolatile memory employing a voltage-driven spintransistor will be described. The same configuration can be adoptedwhere a current-driven type spin transistor is used in a memory cell.

FIG. 6 (A) shows an example of the memory cell using the spintransistor. FIG. 6 (B) shows an example of a memory circuit configuredwith the memory cell. The relationship between FIG. 6 (A) and FIG. 6 (B)is the same as that between FIG. 4 (A) and FIG. 4 (B). In the memorycircuit shown in FIG. 6 (A), a number of spin transistors 150 arearranged in a matrix, with the sources S grounded and the drains D andthe gates G connected to a bitline BL for sensing and a wordline WL forsensing, respectively. A wordline for writing and a bitline for writingare arranged to intersect one another above the spin transistors 150 ina manner electrically insulated from other wires. The wordline forwriting and the bitline for writing may be combined with theaforementioned bitline BL for sensing and the wordline WL for sensing,as shown in FIGS. 6 (A) and (B). In the case of FIGS. 6 (A) and (B), amemory cell can be configured with a single spin transistor, and also avery simple wiring arrangement can be adopted.

Particularly in the case of a voltage-driven spin transistor, which hasa similar form to that of a MOS transistor, a layout suitable formicrofabrication can be easily obtained by, for example, causingadjacent memory cells to use the source in common.

The aforementioned writing/sensing bitlines and writing/sensingwordlines will be hereafter referred to simply as a bitline BL and awordline WL, respectively.

Information can be written over by causing a current to flow through thebitline BL and the wordline WL that intersect over a selected memorycell and then inverting the free layer of the selected memory cell witha composed magnetic field induced by the current through the respectivelines. In order not to allow non-selected cells connected to the samebitline BL or wordline WL as those of the selected cell to be invertedby magnetization, a current value that is caused to flow in each line isset in advance such that no magnetization inversion is caused by amagnetic field emitted by one of the lines.

When sensing information, a voltage is applied to the wordline WL of aselected cell so as to cause the spin transistor to conduct, and then avoltage is applied to the bitline BL to detect the magnitude of thedrain current. Based on the magnitude of the drain current, the relativemagnetization configuration of the free layer and the pin layer can bedetected.

FIG. 6 (B) shows the memory circuit shown in FIG. 6 (A), to a bitlineend of which an output terminal V_(O) is connected, with a branch fromthe output terminal V_(O) connected to a power supply voltage V_(DD) viaa load. FIG. 6 (C) shows the static characteristics and operating pointsof the memory cell shown in FIG. 6 (B). Although an active load 160consisting of a depletion-type MOS transistor is used as the load inthis example, pure resistance may be used, as shown in FIG. 4 (B).Referring to FIG. 6 (C), when sensing information, a gate voltage V_(GS)is applied to the gate of a spin transistor 150 and a power supplyvoltage V_(DD) is applied to the bitline BL via a load. This causes theoperating point due to the active load to move along the load curveshown in FIG. 6 (C) (between P11 and P12) depending on the magnetizationconfiguration between the pin layer and the free layer. As a result, theoutput signal V_(O) would be V_(O↑↑) or V_(O↓↑) for the parallel orantiparallel magnetization, respectively. The absolute values of theoutput signals and their ratio (V_(O↑↑)/V_(O↓↑)) can be optimized usingthe transistor characteristics of the active load or the parameters ofperipheral circuitry, such as V_(DD). For example, by optimizing theintersection of the static characteristics of the spin transistor andthe load curve of the active load, a large output signal ratio can beobtained even when the drain current ratio I_(O↑↑)/I_(O↓↑) is small.Further, even if there are variations in the values of I_(O↑↑) andI_(O↓↑) among memory cells, the fluctuation in the output voltage can bealmost eliminated as long as the saturation current of the active loadis larger than I_(O↓↑) and smaller than I_(C↑↑). Because no senseamplifiers are used for sensing information, a high-speed sensing can beperformed. Thus, the memory circuit of the present embodiment isadvantageous in that output signals of a desired magnitude can be easilyobtained and in that a high-speed sensing can be performed.

In the conventional memory cell utilizing the MTJ and MOS transistors,output voltages produced by the resistance of a MTJ are sensed by asense amplifier. In this case, however, because the output voltage isdetermined by the value of the current through the MTJ and the impedanceof the MTJ (junction resistance), the output voltage ratio cannot befreely adjusted by peripheral circuitry.

In the following, the structure of a spin transistor that can be used inthe nonvolatile memory circuit of the present embodiment will bedescribed with reference to the drawings, using abbreviations FM forferromagnetic metal, FS for electrically conductive ferromagneticsemiconductor, IFS for insulating ferromagnetic semiconductor, and NMfor a nonmagnetic material. In particular, an “NM metal” designates anonmagnetic metal, and an “NM semiconductor” designates a nonmagneticsemiconductor. First, a group of spin transistors of the current-driventype will be described.

FIG. 7 shows an energy band diagram of a hot-electron transistor typespin transistor. A spin transistor 200 comprises an emitter 201 and abase 205 that are formed by FM or FS. Specifically, the spin transistor200 comprises emitter 201 formed by FM (or FS); emitter barrier 203formed by NM; base 205 formed by FM (or FS); collector barrier 207formed by NM; and collector 211 formed by NM. NM may be either anonmagnetic metal or a nonmagnetic semiconductor.

In the spin transistor 200 shown in FIG. 7, spin-polarized hot carriersare tunnel-injected from the emitter 201 to the base 205 via the emitterbarrier 203. When the emitter 201 and the base 205 possess parallelmagnetization, the injected spin-polarized hot carriers hardlyexperience spin-dependent scattering within the base 205. Thus, bysetting the base width such that the carriers can pass through the base205 ballistically, the carriers can be transported beyond the collectorbarrier 207 to the collector 211. This is a transistor operation similarto that of a conventional hot electron transistor.

On the other hand, when the emitter 201 and the base 205 possessantiparallel magnetization, the spin-polarized hot carriers injectedfrom the emitter 201 to the base 205 lose energy due to thespin-dependent scattering within the base 205 and are therefore unableto overcome the collector barrier 207, resulting in a base current.Namely, when the emitter 201 and the base 205 possess antiparallelmagnetization, the current transfer ratio drops as compared with thecase of parallel magnetization. Therefore, even if the same bias isapplied to the spin transistor 200, the current transfer ratio orcurrent gain varies depending on the difference in the relativemagnetization configuration between the emitter 201 and the base 205.The spin transistor 200 can be operated at room temperature byappropriately selecting the collector barrier height, for example.

In the spin transistor 200, if the ratio of the current transfer ratioin the case where the emitter-base junction has parallel magnetizationand that in the case where the junction has antiparallel magnetizationis to be increased, the base width must be sufficiently large so thatthe spin-dependent scattering can effectively function. However, whenthe base width is increased, the current transfer ratio becomes smallereven when the emitter-base junction has parallel magnetization, droppingbelow 0.5, for example. Thus, there is a tradeoff between an increase inthe base width and a decrease in amplification function.

FIG. 8 shows an energy band diagram of a hot-electron transistor typespin transistor in which thermionic emission is utilized as a mechanismfor injecting spin polarized carriers to the base. As shown in FIG. 8, aspin transistor 220 comprises an emitter 221 formed by FM (or FS); abase 225 formed by FM (or FS); and an emitter barrier 223 disposedbetween the emitter and the base and formed by NM. Furthermore, on theopposite side to the junction between the base 225 and the emitterbarrier 223, there is provided a collector barrier 227 formed by NM anda collector 231 formed by NM. The emitter barrier 223 and collectorbarrier 227 may be formed by a nonmagnetic semiconductor. The collector231 may be formed by a nonmagnetic semiconductor or a nonmagnetic metal.

Between the emitter 221 and the emitter barrier 223, an ohmic contact ora tunnel contact is formed. Between the base 225 and the emitter barrier223, and between the base 225 and the collector barrier 227, a junctionexhibiting a band discontinuity as shown in FIG. 9 is formed. This banddiscontinuity can be realized by a Schottky junction between NMsemiconductor and FM, or by a heterojunction between NM semiconductorand FS. Alternatively, a Schottky junction may be formed between FS andFM, and the resultant Schottky-barrier may be used as the emitterbarrier, with FS and FM functioning as emitter and base, respectively.

The spin-polarized carriers diffused from the emitter 221 to the emitterbarrier 223 through the application of a bias to the base 225 withrespect to the emitter 221 are injected to the base 225 as hot carriersby thermionic emission. When the emitter 221 and the base 225 possessparallel magnetization, the spin-polarized hot carriers injected intothe base 225 can reach the collector without being subjected tospin-dependent scattering. However, when the emitter 221 and the base225 possess antiparallel magnetization, the spin-polarized hot carriersare rendered into a base current by spin-dependent scattering. In thistransistor 220 too, because it utilizes spin-dependent scattering in thebase, there is a tradeoff, as in the above-described spin transistor200, between the ratio of the current transfer ratio in the case ofparallel magnetization and that in the case of antiparallelmagnetization, and the current transfer ratio in the case of parallelmagnetization. The transistor 220, however, is advantageous as comparedwith the spin transistor 200, which utilizes tunnel injection, in that alarger current driving force can be obtained and in that a roomtemperature operation can be easily realized.

FIG. 9 shows an energy band diagram of a hot-electron transistor typespin transistor utilizing the spin-filter effect. Although thetransistor has already been described in detail, its characteristicswill be briefly described. A spin transistor 240 shown in FIG. 9comprises an emitter barrier 243 and a collector barrier 247 that areformed by IFS. Via an emitter 241, which is formed by an NMsemiconductor (or an NM metal), the carriers with one spin can beselectively injected into the base 245, which is formed by an NMsemiconductor (or an NM metal), through the spin-filter effect providedby the emitter barrier 243. When the base width is set to be not greaterthan the mean free path of the spin-polarized hot carriers, thespin-polarized hot carriers injected into the base 245 are transportedto the base 245 ballistically. In this case, the spin transistor 240 isbiased such that the spin-polarized hot carriers are injected into theenergy-split width between an up-spin band (a spin band edge designatedby the upward arrow in FIG. 9) and a down-spin band (a spin band edgedesignated by the downward arrow in FIG. 9). When the emitter barrier243 and the collector barrier 247 have parallel magnetization, thespin-polarized hot carriers injected into the base 245 can overcome thebarrier of the spin band of lower energy in the collector barrier 247through the spin-filter effect of the collector barrier 247, andtherefore propagate to a collector 251, which is formed by an NMsemiconductor (or an NM metal). On the other hand, when the emitterbarrier 243 and the collector barrier 247 have antiparallelmagnetization, most of the spin-polarized hot carriers cannot overcomethe collector barrier 247 because of the spin-filter effect of thecollector barrier 247, resulting in a base current.

Thus, in the spin transistor 240, the current transfer ratio (or thecurrent gain) differs depending on the relative magnetizationconfiguration of the emitter barrier 243 and the collector barrier 247.Because the spin-filter effect provides a very high spin-selectivity,the ratio of current transfer ratio in the case of parallelmagnetization and that in the case of antiparallel magnetization can beincreased.

Furthermore, in the spin transistor 240, the base width can be madesufficiently small. Therefore, in contrast to the spin transistor thatutilizes spin-dependent scattering, as in the cases shown in FIGS. 7 and8, the spin transistor 240 is advantageous in that there is no tradeoffbetween the current gain relating to the base width and the spinselectivity.

FIG. 10 shows an energy band diagram of a tunnel base transistor typespin transistor. As shown in FIG. 10, a tunnel base transistor type spintransistor 260 comprises an emitter 261 and a collector 265 that areformed by a p-type (or an n-type) FS, and a tunnel base 263, which isformed by an n-type (or a p-type) NM semiconductor. In the emitter-basejunction and in the base-collector junction, a heterojunction of type IIis preferably used so that the base 263 becomes a barrier to the holes(or electrons). The base width is reduced sufficiently that a tunnelingcurrent from the emitter to the collector is produced.

In the structure shown in FIG. 10, when the emitter 261 and thecollector 265 have parallel magnetization, the carriers with themajority spin in the emitter can be easily transported to the collector265 through tunneling, namely, the tunnel conductance is large. However,when the emitter 261 and the collector 265 have antiparallelmagnetization, the tunnel conductance is reduced by the tunnelingmagnetoresistance (TMR) effect. Thus, the magnitude of the collectorcurrent can be controlled by the relative magnetization configurationbetween the emitter 261 and the collector 265.

If the TMR ratio in the spin transistor 260 can be increased, the changein collector current that depends on the magnetization configurationbetween emitter and collector can be increased. In order to allow theTMR effect to be effectively exhibited in the spin transistor 260, it ispreferable to prevent the depletion layer from expanding towards thecollector when a reverse bias is applied across the base-collectorjunction. It is noted, however, that if the depletion layer is expandedtowards the base, a problem could possibly arise in the collectorcurrent saturation characteristics.

When the base layer in the spin transistor 260 is heavily doped so as toprevent the spreading of the depletion layer and to cause the depletionlayer in the base-collector junction to spread towards the collector,the TMR effect in the base cannot be expected. However, the carriersinjected into the collector are subjected to spin-dependent scatteringin the collector resistance, resulting in increased resistance. Byutilizing this spin-dependent scattering, the magnitude of the collectorcurrent can be varied by the magnetization configuration in theemitter-collector junction. It is possible, however, that the effect isnot so large as that obtained with the TMR effect because the resistancechange through spin-dependent scattering is small.

Hereafter, a group of voltage-driven spin transistors will be describedwith reference to the drawings.

FIG. 11 shows a cross-section of a MOS transistor type spin transistor.As shown in FIG. 11, the MOS transistor type spin transistor 300comprises an NM semiconductor 301 on which a source 303 formed by FM, adrain 305 formed by FM, and a gate electrode 311 are formed, the gateelectrode via a gate insulating film 307. A Schottky junction of FM andan NM semiconductor is used for the source 303 and the drain 305. Theother structures are the same as those of a conventional MOS transistor.

Spin-polarized carriers injected from the source 303 into a channelformed directly below the gate insulating film 307 of the NMsemiconductor 301 pass through the channel to the drain 305 (hereafter,the influence of the Rashba effect due to the gate electric field of thespins injected into the channel will be ignored for simplicity). Whenthe source 303 and the drain 305 have parallel magnetization, thespin-polarized carriers injected into the drain 305 are not subject tospin-dependent scattering. When they have antiparallel magnetization,however, resistance by spin-dependent scattering is produced in thedrain electrode 305.

Thus, in the transistor 300, the mutual conductance differs depending onthe relative magnetization configuration between the source and drain.

The source 303 and the drain 305 may be formed by FS, and a pn junctionis formed between each and the semiconductor 301.

FIG. 12 shows a cross section of a modulation-doped transistor type spintransistor. The spin transistor 320 comprises a source 323 of FM (or FS)in contact with the two-dimensional carriers gas produced at theboundary between a first NM semiconductor 321 and a second NMsemiconductor 327; a drain 325 formed by FM (or FS); and a gateelectrode 331. The spin transistor 320 is identical to a conventionalmodulation-doped transistor with the exception that the source 323 anddrain 325 are formed by a ferromagnet.

Spin-polarized carriers are injected from the source 323 to a channel333 formed by the two-dimensional carrier gas. The spin-polarizedcarriers that reach the drain 325 have different mutual conductancedepending on the relative magnetization configuration of the source 323and the drain 325 due to spin-dependent scattering in the drain 325.

FIG. 13 shows a cross section of a MOS transistor type spin transistorin which the channel region is formed by FS. The spin transistor 340shown in FIG. 13 comprises FS 341 on which a source 343 formed by FM, adrain 345 formed by NM (or FM or FS), and a gate electrode 351 via agate insulating film 347 are formed. A Schottky junction of FM and FS isused in the source 343; except for that, the structure is identical tothat of a conventional MOS transistor.

Spin-polarized carriers are injected from the source 343 into thechannel 341 by tunneling through the Schottky barrier. Based on the TMReffect and the spin-dependent scattering in the channel of FS 341 duringtunneling injection, a mutual conductance that depends on the relativemagnetization configuration of the source 343 and FS 341 is realized.

FIG. 14 shows a cross section of a spin transistor 360 comprising atunnel junction structure in which an insulating NM tunnel barrier 365is disposed between a source 361 formed by FM (or FS) and a drain 363formed by FM (or FS). It is a spin transistor with the gate electrode371 disposed such that an electric field can be applied to the tunnelbarrier 365.

The thickness of the tunnel barrier 365 is preferably set such that noFowler-Nordheim (FN) tunneling occurs when only a source-drain bias isapplied. A triangular potential at the band edge of the tunnel barrierproduced by applying a bias across the source-drain junction is variedby the gate voltage in order to induce FN tunneling and obtain a draincurrent.

Spin-polarized carriers injected from the source 361 are subject tospin-dependent scattering in the drain 363 depending on the relativemagnetization configuration of the source 361 and drain 363. Thus, themutual conductance of the transistor can be controlled by the relativemagnetization configuration between the source and drain.

FIG. 15 shows a cross section of a spin transistor 380, which is similarto the spin transistor 360 shown in FIG. 14 with the exception that thetunnel barrier comprises a tunnel barrier 385 formed by IFS. While asource 381 must be FM or FS, a drain 383 may not be a ferromagnet. Inthe IFS tunnel barrier layer 385, the barrier height differs dependingon the spin direction of the carriers. A bias is therefore appliedbetween the source and drain and across the source-gate junction suchthat the transistor conducts when the source 381 and the tunnel barrier385 have parallel magnetization. Under the same bias condition, when thesource 381 and tunnel barrier 385 have antiparallel magnetization, thetunnel barrier height as seen from the majority spin in the source 381increases. As a result, the tunneling probability of the spin-polarizedcarriers decreases, leading to a decrease in drain current. Because thespin selectivity provided by this spin-filter effect is extremely large,the change in mutual conductance depending on the relative magnetizationconfiguration of the source and drain can be increased by using aferromagnet with a large spin polarization in the source 381.

Any of the above-described various spin transistors may be used as thememory cells for the memory circuit shown in FIG. 4 or FIG. 6.

It is also possible to form a configuration in which the twovoltage-driven spin transistors shown in FIGS. 11, 14, and 15 have acommon source. FIG. 16 (A) shows an example of a memory cell of acommon-source configuration. FIG. 16 (B) shows a cross section of thememory cell of a common-source configuration.

The memory cell structure shown in FIGS. 16 (A) and (B) comprises afirst spin transistor Tr1 and a second spin transistor Tr2 that aredisposed adjacent to one another; a wordline WL connecting a gateelectrode G1 of the first spin transistor Tr1 and a gate electrode G2 ofthe second spin transistor Tr2; a first bitline BL1 connected to a firstdrain D1 of the first spin transistor Tr1; a second bitline BL2connected to a second drain D2 of the second spin transistor; aferromagnetic source S common to the first and second spin transistorsTr1 and Tr2; and a line connecting the common source to ground. In thisconfiguration, the common source makes the cell structure suitable forhigher-density integration.

In particular, the voltage-driven spin transistors shown in FIGS. 11,14, and 15 preferably comprise a highly insulating substrate, such as anSOI substrate as shown in FIG. 16 (B), so as to reduce leakage currentwhen the transistor is off.

As described above, the spin-filter transistor and various spintransistors according to the various embodiments of the presentembodiment are characterized in that the output characteristics can becontrolled by the relative magnetization configuration of the pin layerand free layer within the device. The relative magnetizationconfiguration is nonvolatile, namely, the device does not require thefeeding of power for retaining the magnetization configuration. Thus,the device can store binary information in terms of the relativemagnetization configuration in a nonvolatile fashion. Further, using theaforementioned output characteristics, the relative magnetizationconfiguration can be electrically detected. Thus, a 1-bit nonvolatilememory cell can be configured with a single spin transistor. Using anonvolatile memory circuit comprising a spin transistor according to theembodiments of the invention, the ratio of output signals as well astheir magnitudes with respect to the stored information can be freelydesigned.

Thus, using the spin transistor according to the embodiments of theinvention and a memory circuit comprising the spin transistor, theoperating speed and the level of integration of a nonvolatile memorycircuit can be increased.

While the present invention has been described with reference to variousembodiments thereof, the present invention is not limited by any ofthese embodiments. It should be obvious to those skilled in the art thatvarious modifications, improvements or combinations can be made.

INDUSTRIAL APPLICABILITY

In accordance with the spin-filter transistor of the present invention,the output characteristics can be greatly changed by the relativemagnetization configuration of the ferromagnetic barrier layers.

A nonvolatile memory circuit comprising a memory cell employing thisspin-filter transistor or a spin transistor with equivalentcharacteristics can store binary information in terms of the relativemagnetization configuration of ferromagnets contained in the transistor.The relative magnetization configuration can also be detectedelectrically. Furthermore, using the nonvolatile memory circuit of thepresent invention, the output signals with respect to the storedinformation can be freely designed. Using such a spin transistor, ahigh-speed and high integration-density nonvolatile memory circuit canbe realized that comprises a 1-bit nonvolatile memory cell made up of asingle transistor.

1-70. (canceled)
 71. A transistor comprising: a spin injector forinjecting spin-polarized hot carriers by a spin-filter effect; and aspin analyzer for selecting the thus injected spin-polarized hotcarriers by the spin-filter effect.
 72. The transistor according toclaim 71, wherein said spin injector comprises: a first ferromagneticbarrier layer through which the carriers can be transported by tunnelingupon application of a voltage across said first ferromagnetic barrierlayer; a first nonmagnetic electrode layer joined to one end surface ofsaid first ferromagnetic barrier layer; and a second nonmagneticelectrode layer joined to the other end surface of said firstferromagnetic barrier layer.
 73. The transistor according to claim 71,wherein said spin analyzer comprises: a second ferromagnetic barrierlayer; said second nonmagnetic electrode layer joined to one end surfaceof said second ferromagnetic barrier layer; and a third nonmagneticelectrode layer joined to the other end surface of said secondferromagnetic barrier layer, wherein said second nonmagnetic electrodelayer is common to said spin injector and said spin analyzer.
 74. Thetransistor according to claim 72, wherein said first and secondferromagnetic barrier layers comprise a ferromagnetic semiconductor or aferromagnetic insulator.
 75. The transistor according to claim 72,wherein the thickness of said second nonmagnetic electrode layer issmaller than the mean free path of the spin-polarized hot carriers insaid second nonmagnetic electrode layer.
 76. A transistor according toclaim 72, wherein the spin-filter effect of said spin injector takesadvantage of the fact that, in a carrier tunneling effect in said firstferromagnetic barrier layer which is produced through the application ofa voltage to said first nonmagnetic electrode layer and to said secondnonmagnetic electrode layer, those of the carriers that exist in saidfirst nonmagnetic electrode layer and that have a spin directionparallel to a spin band at the band edge of said first ferromagneticbarrier layer have a large tunneling probability, while those carrierswith an antiparallel spin direction have a small tunneling probability.77. The transistor according to claim 72, wherein the spin-filter effectof said spin analyzer takes advantage of the fact that, when the spindirection of the spin-polarized hot carriers injected from said spininjector is parallel to that of the spin band at the band edge of saidsecond ferromagnetic barrier layer, said spin-polarized hot carriers aretransported through the spin band at the band edge of said secondferromagnetic barrier layer and reach said third nonmagnetic electrodelayer, whereas when the spin direction of said spin-polarized hotcarriers is antiparallel to that of the spin band at the band edge ofsaid second ferromagnetic barrier layer, said spin-polarized hotcarriers are unable to reach said third nonmagnetic electrode layer. 78.The transistor according to claim 72, wherein a first voltage is appliedbetween said first nonmagnetic electrode layer and said secondnonmagnetic electrode layer from a first power supply, and a secondvoltage is applied between said second nonmagnetic electrode layer andsaid third nonmagnetic electrode layer or between said first nonmagneticelectrode layer and said third nonmagnetic electrode layer, from asecond power supply, and wherein said spin-polarized hot carriersinjected from said first nonmagnetic electrode layer to said secondnonmagnetic electrode layer are switched to a current through saidsecond ferromagnetic barrier layer and said second power supply or acurrent through said second nonmagnetic electrode layer and said firstpower supply depending on the relative magnetization configuration ofsaid first ferromagnetic barrier layer and said second ferromagneticbarrier layer.
 79. The transistor according to claim 78, wherein saidfirst voltage is applied such that the energy of the injectedspin-polarized hot carriers becomes larger than the spin band edgeenergy at the band edge of the said second ferromagnetic barrier layerand smaller than the energy of the spin band edge to which thespin-split width is added.
 80. The transistor according to claim 79,wherein the relative magnetization configuration in said firstferromagnetic barrier layer or said second ferromagnetic barrier layercan be reversed with the application of a magnetic field.
 81. A memorycircuit comprising a memory cell formed by the transistor according toclaim
 71. 82. The memory circuit according to claim 81, wherein saidsecond nonmagnetic electrode layer of said transistor is connected to awordline, said third nonmagnetic electrode layer of said transistor isconnected to a bitline, said bitline is connected to a power supply viaa load, and said first nonmagnetic electrode layer of said transistor isconnected to ground.
 83. A memory element comprising: a transistorcontaining a ferromagnet and having output characteristics that dependon the spin direction of carriers (to be hereafter referred to as a“spin transistor”); an information writing means for writing informationwithin said spin transistor by changing the magnetization configurationof said ferromagnet; and an information sensing means for sensing fromsaid output characteristics information stored in said spin transistorin terms of a magnetization configuration.
 84. The memory elementaccording to claim 83, wherein said spin transistor comprises a freelayer having at least one ferromagnet in which the relativemagnetization configuration can be independently controlled, and a pinlayer having a ferromagnet in which the relative magnetizationconfiguration is not changed, wherein one of a first memory state inwhich said free layer and said pin layer have the same relativemagnetization configuration, and a second memory state in which theyhave different magnetization configurations, is retained.
 85. A memoryelement according to claim 84, wherein a single spin transistor storesinformation in terms of the relative magnetization configuration of saidfree layer relative to said pin layer, and wherein information stored insaid transistor is detected using the output characteristics of saidspin transistor, which depend on the relative magnetizationconfiguration of said pin layer and said free layer.
 86. The memoryelement according to claim 84, wherein said spin transistor comprises: afirst electrode structure for injecting spin-polarized carriers; asecond electrode structure for receiving said spin-polarized carriers;and a third electrode structure for controlling the amount of thespin-polarized carriers transported from said first electrode structureto said second electrode structure, wherein said pin layer and said freelayer are included in any of said first to third electrode structures.87. A memory element comprising: a single spin transistor described inclaim 86; a first line connecting said first electrode structure toground; a second line connected to said second electrode structure; anda third line connected to said third electrode structure.
 88. A memoryelement comprising: a single spin transistor according to claim 86; afirst line connecting said first electrode structure to ground; a secondline connected to said second electrode structure; a third lineconnected to said third electrode structure; an output terminal formedat one end of said second line; and a fourth line branching from saidsecond line and connected to a power supply via a load.
 89. The memoryelement according to claim 87, further comprising a first separate lineand a second separate line that intersect one another above said spintransistor in an electrically insulated manner.
 90. The memory elementaccording to claim 89, wherein said first separate line and/or saidsecond separate line are replaced with said second line and/or saidthird line.
 91. The memory element according to claim 89, whereininformation is written by reversing the magnetization of said free layerby a magnetic field induced by causing a current to flow through saidfirst separate line and said second separate line, or through saidsecond line and said third line, thereby changing the relativemagnetization configuration between said pin layer and said free layer.92. The memory element according to claim 87, wherein information issensed using the output characteristics of said spin transistor when afirst bias is applied to said third line and a second bias is appliedbetween said first line and said second line.
 93. The memory elementaccording to claim 88, wherein information is sensed using an outputvoltage that is obtained on the basis of a voltage drop across said loaddue to a current through said load and said spin transistor between saidpower supply and said first line when a first bias is applied to saidthird line.
 94. A memory circuit comprising: a single spin transistoraccording to claim 86 arranged in a matrix; a first line connecting eachfirst electrode structure to ground; a plurality of wordlines commonlyconnecting said third electrode structures of said spin transistorsarranged in the column direction; and a plurality of bitlines commonlyconnecting said second electrode structures of said spin transistorsarranged in the row direction.
 95. A memory circuit comprising: the spintransistor according to claim 86 arranged in a matrix; a first lineconnecting each first electrode structure to ground; a plurality ofwordlines commonly connecting said third electrode structures of saidspin transistors arranged in the column direction; a plurality ofbitlines commonly connecting said second electrode structures of saidspin transistors arranged in the row direction; an output terminalformed on one end of said bitlines; and a second line branching fromsaid bitline and connected to a power supply via a load.
 96. The memorycircuit according to claim 94, further comprising a first separate lineand a second separate line that intersect one another above saidtransistor in an electrically insulated manner.
 97. The memory circuitaccording to claim 96, wherein said first separate line and/or saidsecond separate line are replaced with said wordline and/or saidbitline.
 98. The memory circuit according to claim 96, whereininformation is written by reversing the magnetization of said free layerby a magnetic field induced by causing a current to flow through saidwordline and said bitline, thereby changing the relative magnetizationconfiguration between said pin layer and said free layer.
 99. The memoryelement according to claim 94, wherein information is sensed using theoutput characteristics of said spin transistor when a first bias isapplied to said wordline and a second bias is applied between said firstline and said bitline.
 100. The memory element according to claim 95,wherein information is sensed using an output voltage that is obtainedon the basis of a voltage drop across said load due to a current throughsaid load and said spin transistor between said power supply and saidfirst line when a first bias is applied to said third line.
 101. Amemory element comprising: a first and a second spin transistoraccording to claim 86; a first line connecting the first electrodestructure, which is common to said first and said second spintransistors, to ground; a second and a third line connected to thesecond electrode structure of said first spin transistor and the secondelectrode structure of said second spin transistor, respectively; and afourth line connected to the third electrode structure of said firstspin transistor and the third electrode structure of said second spintransistor.
 102. A memory circuit comprising: a plurality of spintransistors according to claim 86 arranged in a matrix; a first linecommonly connecting to ground the first electrode structures of aplurality of spin transistors arranged in a first row and the firstelectrode structures of a plurality of spin transistors arranged in anadjacent, second row; a first bitline commonly connecting the secondelectrode structures of a plurality of spin transistors arranged in afirst row and the second electrode structures of a plurality of spintransistors arranged in a second row adjacent to said first row in thecolumn direction; a second bitline commonly connecting the secondelectrode structures of said spin transistor in said first row and thesecond electrode structures of said second spin transistors in saidsecond row adjacent to said first row in the column direction; and awordline commonly connecting the third electrode structures of saidplurality of spin transistors in a column direction.
 103. A memorycircuit comprising: a plurality of spin transistors according to claim86 arranged in a matrix; a plurality of first lines each commonlyconnecting to ground said first electrode structures of a plurality ofspin transistors in a first row and those of a plurality of spintransistors in a second row adjacent to said first row in the columndirection, wherein each of said first lines is provided for every tworows; a plurality of first bitlines each commonly connecting said secondelectrode structures of a plurality of said spin transistors arranged ina first row, wherein each of said first bitlines is provided for everytwo rows; a plurality of second bitlines each commonly connecting thesecond electrode structures of a plurality of spin transistors arrangedin a second row adjacent said first row in the column direction, whereinone such second bitline is provided for every two rows of said spintransistors; and a plurality of wordlines commonly connecting the thirdelectrode structures of a plurality of said spin transistors arranged inthe column direction.
 104. The memory element according to claim 90,wherein information is written by reversing the magnetization in saidfree layer by a magnetic field induced by causing a current to flowthrough said second line or said third line with which said firstseparate line or said second separate line have been replaced, orthrough said first separate line or said second separate line that hasnot been replaced thereby, thus changing the relative magnetizationconfiguration between said pin layer and said free layer.
 105. Thememory circuit according to claim 97, wherein information is written orrewritten by causing the relative magnetization configuration betweensaid free layer and said pin layer to be changed by a magnetic fieldinduced by causing a current to flow through said wordline or saidbitline with which said first separate line or said second separate linehave been replaced, or through said first separate line or said secondseparate line that has not been replaced thereby.
 106. A transistorcomprising: a spin injector for injecting spin-polarized hot carriers bya spin filter effect; and a spin analyzer for selecting the thusspin-polarized hot carriers by the spin-filter effect, wherein at leastone of said spin injector and said spin analyzer comprises a barrierlayer formed by a ferromagnetic material.
 107. A transistor comprising:a spin injector for injecting spin-polarized carriers by a spin filtereffect; and a spin analyzer for selecting the thus spin-polarizedcarriers by the spin-filter effect, wherein at least one of said spininjector and said spin analyzer comprises a barrier layer formed by aferromagnetic material.
 108. A transistor comprising: an emitter formedby a ferromagnetic material; a base formed by a ferromagnetic material;a collector formed by a nonmagnetic material or a ferromagneticmaterial; a first barrier layer comprising a nonmagnetic materialdisposed between said emitter and said base; and second barrier layercomprising a nonmagnetic material disposed between said base and saidcollector, wherein spin-polarized carriers are injected from saidemitter to said base by Fowler-Nordheim tunneling.
 109. The transistoraccording to claim 108, wherein said emitter and said base are formed bya ferromagnetic metal or a ferromagnetic semiconductor.
 110. Thetransistor according to claim 108, wherein said emitter and said baseare formed by a ferromagnetic semiconductor, and said firs and secondbarrier layers are formed by a semiconductor.
 111. The transistoraccording to claim 108, wherein a room temperature operation is enabledby adjusting the barrier height of said first barrier layer and saidsecond barrier layer.
 112. The transistor according to claim 108,wherein the current transmission rate of the carriers injected from saidemitter to said base depends on the relative magnetization directions ofsaid emitter and said base.
 113. A transistor comprising: an emitterformed by a ferromagnetic material; a base formed by a ferromagneticmaterial; a collector formed by a nonmagnetic material or aferromagnetic material; a first barrier layer disposed between saidemitter and said base; and a second barrier layer disposed between saidbase and said collector, wherein spin-polarized carriers are injectedfrom said emitter to said base by thermal release.
 114. The transistoraccording to claim 113, wherein said emitter and said base are formed bya ferromagnetic metal or a ferromagnetic semiconductor, and said firstand second barrier layers are formed by a semiconductor.
 115. Thetransistor according to claim 113, wherein said emitter and said firstbarrier layer are formed using an ohmic contact or a tunnel contact.116. The transistor according to claim 113, wherein a barrier structurebetween said base and said first barrier layer is formed by a Schottkyjunction when said base is a ferromagnetic metal, or by a banddiscontinuity between said base and said first barrier layer when saidbase is a ferromagnetic semiconductor.
 117. The transistor according toclaim 113, wherein a barrier structure between said base and said secondbarrier layer is formed by a Schottky junction when said base is aferromagnetic metal, or by a band discontinuity between said base andsaid second barrier layer when said base is a ferromagneticsemiconductor.
 118. The transistor according to claim 113, wherein saidemitter is formed by a ferromagnetic semiconductor, said base is formedby a ferromagnetic metal, and said first barrier layer is formed by aSchottky barrier that is formed between a ferromagnetic semiconductorand a ferromagnetic metal.
 119. The transistor according to claim 113,wherein the current transmission rate of the carriers injected from saidemitter to said base depends on the relative magnetization directions ofsaid emitter and said base.
 120. A transistor comprising: an emitterformed by a ferromagnetic semiconductor of a first conduction type; acollector formed by a ferromagnetic semiconductor of a second conductiontype; and a base formed by a nonmagnetic semiconductor of a secondconduction type different from said first conduction type, wherein thewidth of said base is adjusted to be such that a tunneling of thecarriers from said emitter to said collector can take place.
 121. Thetransistor according to claim 120, wherein the emitter-base junction andthe base-collector junction are formed by a heterojunction of type IIsuch that said base forms a tunnel barrier with respect to the majoritycarriers of said emitter and said collector and said emitter and saidcollector form an energy barrier with respect to the majority carriersof said base.
 122. The transistor according to claim 120, wherein themagnitude of mutual conductance or output current can be controlled bythe relative magnetization directions of said emitter and saidcollector.
 123. A transistor comprising: a ferromagnetic semiconductorlayer; a source and a drain formed with respect to said ferromagneticsemiconductor layer; and a gate electrode formed with respect to saidferromagnetic semiconductor layer, wherein at least one of said sourceand said drain is formed by a ferromagnetic material.
 124. Thetransistor according to claim 123, wherein the ferromagnetic materialused in at least one of said source and said drain is a ferromagneticmetal or a ferromagnetic semiconductor.
 125. The transistor according toclaim 123, wherein at least one of said source and said drain is formedby a Schottky junction of a ferromagnetic metal and said ferromagneticsemiconductor layer.
 126. The transistor according to claim 123,comprising a gate insulating layer disposed between said ferromagneticsemiconductor layer and said gate electrode.
 127. The transistoraccording to claim 123, wherein the magnitude of mutual conductance oroutput current can be controlled by the relative magnetizationdirections of said source or said drain and said ferromagneticsemiconductor material.
 128. A transistor comprising a tunnel junctionstructure and a gate electrode, wherein said tunnel junction structurecomprises: a tunnel barrier formed by an insulating nonmagneticmaterial; a source formed by a ferromagnetic material; and a drainformed by a ferromagnetic material, said tunnel barrier being disposedbetween said source and said drain, wherein said gate electrode isformed with respect to said tunnel barrier.
 129. The transistoraccording to claim 128, wherein the ferromagnetic material used in saidsource and said drain is said ferromagnetic metal or a ferromagneticsemiconductor.
 130. The transistor according to claim 128, wherein thethickness of said tunnel barrier is set to be such that a tunnel currentcan take place from said source to said drain with the application of avoltage to said gate electrode.
 131. The transistor according to claim128, wherein the magnitude of mutual conductance or output current canbe controlled by the relative magnetization directions of said sourceand said drain.
 132. A transistor comprising: a tunnel junctionstructure and a gate electrode, wherein said tunnel junction structurecomprises: a tunnel barrier formed by an insulating nonmagneticmaterial; a source formed by a ferromagnetic material; and a drainformed by a nonmagnetic material or a ferromagnetic material, saidtunnel barrier being disposed between said source and said drain,wherein said gate electrode is formed with respect to said tunnelbarrier.
 133. The transistor according to claim 132, wherein theferromagnetic material used in said source or said drain is aferromagnetic metal or a ferromagnetic semiconductor.
 134. Thetransistor according to claim 132, wherein the thickness of said tunnelbarrier is set to be such that a tunnel current can take place from saidsource to said drain with the application of a voltage to said gateelectrode.
 135. The transistor according to claim 132, wherein themagnitude of mutual conductance or output current can be controlled bythe relative magnetization directions of said source and said tunnelbarrier.
 136. A memory element comprising: one transistor according toclaim 106; an information rewriting means for rewriting information insaid transistor by causing the magnetization state of a ferromagneticmaterial contained in said transistor; and an information reading meansfor reading the information stored in the form of a magnetization state,from the output characteristics of said transistor.
 137. The memoryelement according to claim 135, wherein the transistor comprising a spininjector for injecting spin-polarized hot carriers by a spin filtereffect; and a spin analyzer for selecting the thus spin-polarized hotcarriers by the spin-filter effect, wherein at least one of said spininjector and said spin analyzer comprises a barrier layer formed by aferromagnetic material further comprises a free layer having aferromagnetic material in which the direction of magnetization can beindependently controlled, and a pin layer having a ferromagneticmaterial in which the magnetization direction is not changed, wherein afirst state in which said free layer and said pin layer have the samemagnetization direction, and a second state in which they have differentdirections of magnetization can be retained.
 138. A memory elementcomprising one transistor according to claim 106, wherein informationcan be stored based on the magnetization direction of said free layerrelative to that of said pin layer, and the information stored in saidtransistor can be detected based on the output characteristics of thetransistor that depend on the relative magnetization directions of saidpin layer and said free layer.
 139. A memory element comprising: onetransistor according to claim 108; a first line connected to saidemitter; a second line connected to said base; and a third lineconnected to said collector.
 140. A memory element comprising: onetransistor according to claim 123; a first line connected to saidsource; a second line connected to said gate; and a third line connectedto said drain.